Ultrasonic Pulser Receiver Module
Welcome to The Capulin Project,
the design blog for an Ultrasonic Pulser/Receiver meant for use in
the Non-Destructive Testing industry.
Feel free to comment, offer hints, or even help. The newest entry is at the top of this page.
To start reading from the beginning, click
posts Main Page
March 15, 2012
following are the power requirements for the Quad UT Board, version 1.1:
||Typical During Run
April 16, 2010
Printing is Hard
if not most, charting systems on the market do a poor job of printing.
They often do not accommodate different printers very well, sometimes
require special printer drivers, and rarely allow the printout to be scaled
for the best clarity.
Most of these shortcomings are due to the fact that the printing features of
most software development packages are very complicated and the
documentation is obfuscated. Printing a simple picture or a small
amount of text is easy - anything beyond that is always difficult.
Sometimes third-party software packages can be used to ease the task, but
the Capulin Project developers are averse to such solutions because they
make future upgrades problematic (read
more on that).
The printing feature for the Capulin Project is especially
difficult because of the flexibility allowed in regard to the number and
length of charts. The software must be able to scale, separate, and
handle multiple page prints for a nearly endless variety of layouts.
Like other languages, Java offers some nice printing
features - but things get complicated in a hurry.
Click here to continue
November 18, 2009
is the first picture of a full chassis - forty channels in one box!
A forty channel system consisting of a UT chassis, blade computer, filtered
blower, and rack mounted un-interruptible power supply can easily fit into a
cabinet with less than two feet of panel space.
The system has no problem with overheating. This is due to the use of
the latest components; manufacturers constantly work to reduce power
consumption so staying up with the latest technology allows the use of these
more efficient parts.
Additionally, many systems fail not because the components are beyond their
temperature range but because the timing is too tight to allow for any
leeway. The speed of electronic systems varies with temperature.
If all timing is planned in such a way as to anticipate changes in
temperature, a system can run properly at all expected ranges.
November 17, 2009
chassis with 40 ultrasonic channels in operation has been measured as
pulling 1.770 amps at 120 VAC.
Turning off the pulser for various channels reveals that each pulls
approximately .004 amps at 120 VAC.
The difference in current draw at the AC input for all 40 channels on or off
is .157 amps.
The DC amperages have not yet been measured.
June 5, 2009
Java is Cool!
choice of Java for the host software has turned out to be a winner
on so many levels!
The entire program can be packaged into a single, compressed file
and run from a memory stick. That is so cool! No
installation and no program specific DLLs to clutter things up.
A memory stick can be attached by a stretch cord to any product
which links with the software and the user can simply plug the stick
into their computer and instantly run the program.
The program will run on any computer with Java installed.
Using the memory stick has been very handy while debugging. To
update the test computer, it is only necessary to copy the new
program version (one small file) to the memory stick and then plug
it back into the test computer.
One of the driving forces behind the design of Java was the
elimination of features which often resulted in egregious software
crashes, such as memory leaks and array overruns. These
improvements have already saved more than a few hours on this
Of course the program will also run on Microsoft, Sun, Apple, and
Quick and simple!
June 1, 2009
A few glitches have been detected and solved:
- We chose a simple four gate op-amp to drive the MosFet switches.
This op-amp cannot provide an adequate slew rate when more than one
channel is fired simultaneously. To work around this problem until
a new op-amp can be selected, the FPGA has been programmed to provide a
very small delay between channels when firing.
- There is an unexpected ripple on the -3.3 volt supply. It is
unknown if this is coming from the switching power supply or from
something on the board. It is not causing any problem, so it is
not being addressed at this time.
- Four pins on the FPGA seem to be blown. A designer did
experience a static shock discharge to the top of the FPGA package and
the damaged pins are near the edge. The pins are used to read the
chassis and slot address switches on the motherboard. They are not
absolutely necessary and a temporary software work around has been
devised. Better static protection measures have been implemented.
May 25, 2009
Schematics for Version 1.0
schematics for Version 1.0 are now available online in PDF format:
Quad UT Board
Ver 1.0 Schematics
The link is also available in the navigation bar at the left side of
Our policy is to provide as much information as possible to our
customers so that they can make the most efficient and extensive use
of the product as is possible.
One of the reasons we chose the Rabbit module is the amount of
information provided with that system. Schematics, parts
lists, and source code is freely available from the manufacturer.
That knowledge allowed us to quickly address issues which popped up
that would not have been covered in typical documentation.
We want our customers to have that same level of service.
May 15, 2009
Hardware Patches for Version 1.0
The only patch required to Version 1.0 is a single cut trace and the
addition of a resistor.
Boards such as this are very difficult to patch due to multiple layers,
tiny traces and components, and inaccessible connections underneath the BGA
package of the FPGA.
The most amazing thing is that all the components fit onto their pad
layouts. With all the various form factors used, fitting errors are
April 30, 2009
We received the first board for testing. It has just
over 530 components and a few thousand solder connections.
The board has 12 layers, 5 mil line widths with 5 mil
spacing, and an immeasurable amount of blood, sweat, and tears.
The blank board was manufactured by
Gemini Circuits and assembled by
PPSI, both located in
Houston, TX. These two companies are the finest I have ever worked
with and we owe them a lot for their dedication to perfection and their
Four Channel Ultrasonic Pulser
4 channels per board
2 KHz pulse rep rate per channel
10 boards per chassis for 40 channels per
Multiple chassis may be linked for
increased channel capacity
2 Texas Instruments TMS320VC5441 DSPs with
4 DSP cores each
2 DSP cores per channel
Each core executes at 10 nano-seconds per
Overall execution rate is 800 million
instructions per second per board
Channels may be fired simultaneously,
sequentially, or in multiple banks
Pulser voltages available from 150 – 200V
April 10, 2009
board will require some very tight spacing and small holes beneath the FPGA.
The board manufacturer has specified that no more than 12 layers can be used
or the tiny drill bits required may wander too much. The layout has
been tweaked to accommodate this limitation.
The manufacturer also specified a hard limit of 5 mil line widths and 5 mil
spacing. The board was laid out with Eagle and passed the DRC check.
When the manufacturer checked the board with their Gerber software,
ViewMasterEZ, it flagged several spacing errors.
I purchased a copy of ViewMasterEZ and found the same errors.
Apparently, the two programs use slightly different algorithms and/or
rounding to calculate the spacing. Since the manufacturer uses
ViewMasterEZ to make the final decision on manufacturability, it is
necessary to make the board pass that program's DRC.
The following settings were used in ViewMasterEZ and the board was tweaked
in Eagle until it passed with no errors:
The manufacturer routinely removes unconnected inner pads if they are
causing a spacing error. Since we were able to catch all errors, we
were able to correct them beforehand and they did not have to fix anything.
This extra DRC check using the same program as the manufacturer was never
necessary before because our tolerances where much larger, often 12 mil / 12
mil. Even if our program did not calculate the spacing in the exact
same way as that used by the manufacturer, there was enough overage that it
When working at the limits of the manufacturer, it becomes necessary to
perform a more rigorous design rule check.
December 10, 2008
is the Darth Vader of power supplies. We were looking for a heavy duty
supply, and this will do nicely. The cables and connectors are very
rugged and the cooling fan looks like the prop from a P-38. At 750W,
it is not the largest so we can actually move upwards if we need to in the
future. The form factor is standard for a PC chassis so it will fit
into our case with no problem.
We are going to cut the output connectors off and connect to terminal strips
in the chassis. From there power will be routed to terminal lugs on
the motherboard. Reports from the field regarding similar equipment
point out that the standard PC power connectors tend to fail under extremely
December 10, 2008
This is an overview of various timing data and specifications for the
pulser/receiver board and the overall system.
A/D sample rate: 66.666666 million samples/sec
A/D sample rate period: 0.015 us : 15 ns
The A/D clock is used to drive the A/D converters, the FPGA, and the DSP.
Minimum period for clock in of the DSP: 20 ns
Since the A/D clock is too fast for input to the DSP, it will be divided by
two in the FPGA to obtain a 30 ns period. Inside the DSP, it will be
multiplied by 3 by using the PLL to obtain a 10 ns period.
Actual clock period of the DSP: 10 ns
Click here to continue
December 10, 2008
Pulser/Receiver Board Overview
pulser/receiver (UT) board will handle up to four transducers and provide
pulsing, receiving, filtering, data manipulation, and peak detection.
The peak data recorded will be sent to the master or the host PC when
requested, at which time the stored peak will be reset and a new peak
recorded. Click here to continue
December 9, 2008
RCM4200 Memory Management
A Rabbit RCM4200 module will be plugged onto each UT board to provide
control and handle the ethernet link to the master board and the host PC.
The Rabbit has thus far proven to be an excellent system, but a bit
complicated when it comes to understanding the memory management.
In order to fully understand the workings of the system, it is necessary to
untangle the secrets of the memory management system.
Click here for a
October 14, 2008
Typical filter frequency response roll off curves:
1st order -6 dB per octave
2nd order -12 dB per octave
3rd order -18 dB per octave
4th order -24 dB per octave
5th order -30 dB per octave
6th order -36 dB per octave
An octave has nothing to do with the number "eight". An octave is a
doubling (or halving) of the frequency. For a 1st order filter with a
cutoff frequency of 1Khz:
From 1 KHz to 2 KHz, the attenuation increases to -6dB. From 2 KHz to
4 KHz, the attenuation increases to -12dB. For 4 KHz to 8 KHz, the
attenuation increases to -18dB, and so on.
In music an octave is defined as every time the frequency of a note doubles,
as in c4 to c5 on the piano.
June 24, 2008
Performance Requirements Update
ultrasonic testing applications require a water path of 6 inches or longer
between the transducer and the test piece. Regardless of how fast the
electronics are, the sound signal must make it through the wedge or block if
one is used, the water path, the test piece, and back again before the
transducer can be fired again. Of these three materials, water
provides the slowest sound transmission and is generally the limiting factor
for the maximum repetition rate.
A reasonable top end rep rate target is that required to achieve "forty
thousandths pulse density", or one pulse for every 0.04" of travel at 400
feet per minute of product feed rate.
400 ft/min * 12 inch/ft = 4800 inch/min
4800 inch/min / 60 sec/min = 80 inch/sec
80 inch/sec / 0.04 inch/pulse = 2000 pulse/sec = 2K rep rate required
If a ring of transducers having a fixed diameter is utilized, a 16" ring can
be used to inspect tubes from 14" diameter down to 4" diameter while not
exceeding a water path distance of 6". The water path for the 14" tube will be
1" while the water path for the 4" tube will be 6".
The 6" water path, 0.04" pulse density, and 400 fpm feed rate will be used
as a reasonable goal for the project. This goal shall be met for a 40
channel system by multiplexing - alternately firing two banks of 20 channels
each, 2 channels per board. Such a system will require 10 quad channel
If the parameters specified above are to be exceeded, the required pulse
density can be met by reducing the water path (using a smaller transducer
ring for smaller tube diameters), slowing the feed rate, or using more UT
Maximum Rep Rate for Compression Wave
Maximum Rep Rate for 45° Shear Wave
The full path shown in red is one "skip".
The first half of the path is "Leg 1", the second half is "Leg 2".
The transducer angle to the surface of the tube is not 45°,
it is angled appropriately to produce the 45° angle in the tube body taking
into account Snell's Law of Refraction.
June 24, 2008
Choosing Form Factors - Part 2
to increased performance criteria for the CPLD, it is necessary to switch to
an FPGA which is only available in a BGA package. This will complicate
board assembly, troubleshooting, and repair, but is an inevitable choice
driven by technology.
The reasons for the required increase in performance are detailed
June 24, 2008
can now track the progress of the project on twitter. Visit
http://www.twitter.com/capulinproject for concise updates.
You no longer have to scan the entire blog looking for new info, all changes
will be logged on the twitter page. The updates will even show the
time they were logged, making it easier to tell when new information is
Also, twitter will send text alerts to your mobile phone or Instant
Messenger service whenever an update is added.
June 6, 2008
the pins in the CPLD can be pre-assigned, it is highly recommended by the
manufacturer that the designer apply at least a preliminary design to the
CPLD layout software and let it assign the pins the first time through.
This ensures that all logic and timing constraints can be met.
Afterwards, the designer must lock the pins because the board will be laid
out with specific pin functions in mind. Future changes to the CPLD
will be forced to use the same pins.
The following is the proposed operations sequence:
All connections between the Rabbit, DSPs, A/D Converter, Hardware Gain, and
Pulser will be made via the CPLD.
Startup - Rabbit resets DSPs and transfers code to each DSP from the
host computer via Ethernet.
Setup - Rabbit loads appropriate ultrasonic settings into the CPLD
and DSPs - hardware gains, pulse length, processing options
(rectification/polarity, DAC, gates, etc.). Stores the starting memory
and frame length values in each DSP so that it knows where to look for data.
- Rabbit sets 16 bit Delay Counter in CPLD with user specified value
- data points will not be taken after the main bang until this counter
- Rabbit sets 16 bit Frame Length Counter in CPLD - this specifies
how many data points to store in the DSP.
- Rabbit sets 16 bit address counter in CPLD to specify memory
location in DSP to begin storing data.
- Rabbit sets Pulse Enable flag in CPLD and resets the Transfer
- The Pulse Enable flag transfers connection of the DSP's HPI port
from the Rabbit to the A/D input register.
- CPLD waits until the Bank Pulse Sync signal goes low and latches the
Transfer Enable flag low. The Bank Pulse Sync signal is provided to
all boards in the system by the Control I/O board so that all
transducers which are fired simultaneously (bank fired) will do so at
the exact same time. This is necessary to prevent the high voltage
pulse from cross talking to another channel when it is trying to listen
for the very low voltage return signal. If all channels fire
simultaneously, they will be noisy and quiet at the same times.
- Once the Transfer Enable flag is latched low, each 11 bit data word
from the A/D converter is latched into a register in the CPLD on the
rising edge??? of the A/D clock. The upper 5 bits are forced by
the CPLD to logic '1'.
- As each A/D data word is latched, the address counter is incremented
and the frame length counter is decremented.
- Each A/D data word is written to the DSP via its HPI port using the
address counter to determine the location.
- When the frame length counter reaches zero, the Transfer Enable flag
is cleared, the Transfer Complete flag is set, and no more data is
- The DSP will have been looping and monitoring the high bit of the
last memory location of the data frame, having preset this value to
zero. The DSP knows which address to monitor because the Rabbit
has previously transmitted the starting address and frame length.
Because the CPLD forces the 5 upper bits of the data words to '1', the
DSP will be alerted that the data transfer is complete when the top bit
of the last value gets set at that time.
- The DSP will process the data (up-sampling, filtering, attenuating,
adjusting gates to follow the interface, applying DAC, capturing the
peak value in the gates). Upon completion, the peak data will be
stored in a buffer for retrieval by the Rabbit or transmitted via serial
- After processing the data, the DSP will re-enter the wait loop until
more data is available.
- During the data transfer period, the Rabbit will monitor the
Transfer Complete flag in the CPLD to determine when the transfer is
finished. The Rabbit will then clear the Pulse Enable flag which
will transfer connection of the DSP's HPI port back to the Rabbit.
- At that time, the Rabbit will transfer peak data from the DSP which
handled the previous pulse/receive cycle - the currently active
DSP will still be processing its data.
- The Rabbit will setup and trigger the pulse/receive cycle for the
next channel and its associated DSP.
Peak Data Collection - The Rabbit on the control I/O board will
query the Rabbit on each UT board via Ethernet every 0.1 seconds or less to
obtain the peak data it has collected since the last query. The peak
data will be tagged with its channel number and passed to the host via
Ethernet along with the current positioning information obtained from the
encoders. The Control I/O board handles the encoder inputs directly,
tracking the forward and reverse pulses with a counter. The host
computer uses the count from two encoders to determine the location of the
test piece in the system.
|Mon Jun 9 23:23:39 2008 Curt Irvin
I've been reading through the project page and one question that
comes up is about the power supply. What was the planned supply for
boards? Another question I have is when the data has been
manipulated inside the DSP there are two options for transmission.
One is on the ethernet link and the other is serial. Is the serial
just for debugging? I have been doing some refresher reading about
VHDL and was wondering which language should I lean towards (VHSIC
Should I be posting these questions on the page or should I email
Tue Jun 10 00:19:38 2008 Mike Schoonover
re: Power supply, serial transmission, VHDL, posting questions.
The chassis tentatively selected to hold multiple UT boards is an
off-the-shelf PC computer style chassis. Hopefully we can use a
standard supply that fits in that chassis to provide +5V and +12V.
On each UT board we can drop this down to 3.3V and other voltages as
necessary using simple linear regulators.
For a single UT board used in standalone mode, a simple +5V/+12V
switching power supply could be combined in an enclosure along with
Ethernet is being used for communication between the main display
computer and the Control I/O board. The Control I/O board is using
Ethernet to accumulate peak data from each UT board. The display
computer can also talk directly to any UT board via Ethernet for
A Rabbit microcontroller will be placed on each UT board to handle
the Ethernet connection and to control the pulsing and data
collection from the DSPs - of which there are 4 cores located inside
a single chip, one chip to be placed on each board to provide 4 DSPs
with one assigned to each UT channel.
There are two ways to communicate between the Rabbit or the A/D
converter and the DSPs - the single parallel HPI interface for each
DSP chip and the high
speed serial ports of each DSP core. Regardless of the communication
method, all data between the Rabbit or the A/D converter will go
through the CPLD which can handle simultaneous data paths.
The HPI port is the fastest way to stuff or retrieve data into and
from the DSPs - one 16 bit data path with access to all memory of
any core in the chip. Since the data from the converter will be
transferred at 66mHz, this seems to be the best choice for that
The transducers need to be fired and processed with as high a
repetition rate as possible ~ 2.5 kHz for each channel or faster.
Since there is only one HPI port, it cannot be used by both the A/D
converter to feed data and the Rabbit to read peak data at the same
time. So the Rabbit cannot read the peak data from a DSP which has
just finished processing data while the next DSP is being fed new
data unless a second access method is used.
A second access method does exist - each DSP has a high speed serial
port which could be used by the Rabbit to access completed data
while new A/D data is being fed into the currently active DSP. This
would improve the repetition rate because there would be no delay of
starting the next conversion sequence as a result of transferring
data to the Rabbit via the HPI port.
However, the serial ports use a lot of pins and it would be fairly
complex. Normally the data transferred to the Rabbit would be small
- just the peak data from each gated area, less than 100 bytes
total. This would have an inconsequential effect on the rep rate. It
is also planned to periodically transfer a snapshot of the entire UT
signal of a single pulse from each DSP so that it can be displayed
to give a visual cue as to how each channel is operating. This would
require 10k - 20k of data transfer between the Rabbit and the
selected DSP in the rotation.
It is probable that a data transfer of this size would also have a
negligible affect on the rep rate because it is a parallel transfer.
If it turns out to be a problem, the transfer could be segmented so
that it could be distributed over time - a smaller transfer between
each pulse initiation. The snapshot data is not time critical as it
is for evaluation purposes only.
At this time, due to the complexity of the serial ports and the high
speed of the HPI port, is is proposed that the HPI port be used for
all data transfer. The transfer of peak data to the Rabbit will be
interleaved with the transfer of A/D data from the converter.
I don't have enough knowledge to answer this question for sure at
this time. My understanding is that there are two main flavors: VHDL
and Verilog. Verilog is a language created by a specific company
while VHDL is the open standard created later to remove commercial
bias and give control to an independent committee. I don't know how
VHSIC relates to these two.
While VHDL has the reputation of being a bit more technical and less
user friendly, it would seem to be a good choice due to its control
by an independent group. The hope is that it would be more
transferable between companies.
A third option is supported by
Xilinx and some other CPLD manufacturers - schematic entry.
While the schematic is not transferable between companies, I
believe that the compilation process produces a VHDL file
translation of the schematic which would be transferable. The
advantage of the schematic method is that it uses industry standard
symbols and gates which everyone can understand.
Some elements are
far easier to implement in VHDL rather than in a schematic - a 32x32
multiplier for example. These can be created in VHDL and then
incorporated into a schematic as an object, providing the best of
The CPLD evaluation board I have ordered for you uses VHDL
and schematic entry in a
simple project. Hopefully that will give you a little more input.
It is great to post questions to the blog as they often help other
project members clarify their own knowledge and it brings all issues
out in the open. Hopefully, at the end of the project no one is
saying "What? You are using xyz protocol do do what??!!"
June 6, 2008
In an earlier post, the decision to
use the Rabbit microcontroller was discussed. Further research has
verified the validity of this concept. As the DSPs have no simple way
to write data to off-chip locations, other than via serial, they are not a
good choice for setting up registers in the CPLD to trigger a pulse/receive
sequence. The DSPs are designed to be pushed data from outside and
triggered to work on that data - they do not have the facilities to actively
collect the data.
Thus the Rabbit will be the main controller on the board, setting up
registers in the CPLD and DSPs and triggering each pulse/receive sequence.
June 4, 2008
New Contributor Announcement
are pleased to announce that Fiona Zhang has joined the team as a
contributing member! Fiona has a masters degree from the University of
Houston and isn't afraid to tackle ANY problem! Currently, her focus
is on database development and management, but I personally know that she
has dabbled in the exciting world of 3D graphics. I once gave her a
very dry textbook on the subject (which she had never studied before) and a
few weeks later she had some working code. Fiona's thesis involved
high speed data distribution over TCP/IP networks, similar to the work we
are planning with Ethernet.
Please join us in welcoming Fiona aboard!
|Thu Jun 5 17:26:06 2008 T Ray
Welcome to the team Fiona. Above all, have FUN!
June 4, 2008
Calculating Hardware Gain Stages
All DSP systems would be simpler if they didn't require adjustable hardware
gains. Unfortunately there is an inherent limitation in Discrete
Digital Signal Processing which requires that the input signal be adjusted
to the maximum possible level before A/D conversion. If your signal
input has a wide dynamic range, it is nearly impossible to avoid using
adjustable hardware gains.
After the signal is digitized, amplifying does not work very well. On
the other hand, attenuating the signal works fine. This is because the
signal is composed of discrete, granular values once it is in the computer
If the signal is very small compared to the full range of the A/D converter,
for example the amplitude is the value "5", amplifying the signal results in
a "stair step" effect. For instance, when the signal is 2 and it is
multiplied by 10 you get twenty. If the signal moves to 3, a single
count, and it is multiplied by 10 you get 30. So the resulting signal
jumps 10 counts for just 1 count of change on the input. This is
because the signal has been quantized - it cannot range between 2 and 3 but
can only jump from one to the other. If the output is displayed on a
scale of 1 pixel per count, the output will seem to jump back and forth 10
pixels when the input changes by a single count.
Attenuation works fine - a bigger number gets squeezed smaller. If two
input values get rounded off to the same value, it looks fine and is not
noticeable. Thus if the biggest signal to be expected is hardware
amplified to the full input span of the A/D converter, it can always be
attenuated in software.
|Decibel and Gain Relationships
dB = 20 log (Va/Vb)
To convert gain
to decibels, take the log of the gain and multiply by 20.
To convert decibels to gain, divide the decibels by 20 and take the
Gain of 1 (va = vb) -> 0dB
Gain of 2 (Va = Vb * 2) = 6dB
Gain of 16 = 24dB
Gain of 32 = 30dB
Gain of 40 = 32dB
Gain of 100 = 40dB
Gain of 3162 = 70dB
Gain of 10,000 = 80dB
3162 = 16 * 197 (gain of two stages for total gain of 3162)
3162 = 16 * 16 * 12 (gain of three stages for total gain of 3162)
1mV to 2V = Gain of 2000
Gain of 2000 = 66dB
The LMP8100 is an adjustable gain op-amp, with 16 selections
ranging from a gain of 1 to a gain of 16. Two can be cascaded to give
256 possible gain values.
Using a first stage gain of 12 followed by two LMP8100s w/max
gain of 16 gives a total max gain of (above calculations were rounded off, the
following is exact):
12 * 16 * 16 = 3072 Max Gain
Max Gain 3072 = 69.7dB
In this case the smallest gain (and step size) is 12
A typical maximum gain for a UT instrument is 70 - 80db.
Many systems have a gain setting range of 80dB with a step as
little as 0.3dB. This can be a bit misleading because a 0.3dB step at
the low end is quite small while a 0.3dB step at the high end is huge as
Decibels is a log function. Thus the granularity of the gain
adjustment goes from very fine to very crude along the entire span of the
To clarify this, the following shows a 1dB change from 1dB to
2dB and how it differs as the dB value becomes larger:
1 to 2 dB = gain change of 0.13 (1.25 - 1.12)
5 to 6 dB = gain change of 0.22 (1.99 - 1.77)
79 to 80 dB = gain change of 1,088 (10,000 - 8,912)
Since the industry standard is gain adjustment in decibels, our software
will do the same. As the user adjusts the gain in decibels, the
software will convert it to gain and calculate the appropriate settings for
the two adjustable gain op-amps. The square root of the gain will be
taken to determine the settings for each op-amp so that each carries the
gain load nearly equally. If the square root is not an integer, the
value will be rounded down and used for the first op-amp. The second
op-amp will be set so that the total gain matches the dB setting.
|Wed Jun 4 20:10:50 2008 Trey Brown
I agree. Gain should be a preset or MAX coming into the system.
Attenuation is the control. Don't forget about the DAC Curve.
Wed Jun 4 20:27:05 2008 Mike Schoonover
The DAC curve is on the main feature list. It's probably time to
make an entire page devoted to the planned features for the
prototype so we all know what we are aiming for.
June 3, 2008
If you've read Dreaming in Code by Rosenberg on my suggested
reading list, you're familiar with the quagmire of feature creep.
Feature creep is when more and more features get added to the project while
it's underway, pushing the time-to-market farther and farther into the
Of course, most feature creep is always blamed on marketing but sometimes
it comes from the design team. It is a constant battle to stay focused
when new ideas pop up.
As the A/D converter is a dual device, it was considered to use two of
the chips - one A/D for each channel - rather than use a mux to switch the
four channels into one converter. With this method, it might even be
possible to pulse all four channels at once.
As it turns out, there is only one 16 bit channel to get data into the
DSP - the HPI port. If all four A/D converters are running at once,
four data words would have to be stuffed into the DSP for each clock cycle -
a questionable process at 66Mhz. Even worse, it would have taken 44
inputs on the CPLD.
Next, it was considered to use each A/D converter in one package to
handle two channels, using two muxes. This still would have required
double data transfer unless the 11 bit words from each converter were
truncated to 8 bits and handled as a single word. For this scenario,
22 inputs would have still been required on the CPLD to preserve the 11 bits
for times when only one A/D converter was used at a time.
All of this would have required significant extra logic in the CPLD and
two to four times the amount of analog circuitry. It was decided that
this was way too much work for a feature which might never even be needed.
Being able to gang fire a single channel on each board in a multi-board
system is already a powerful feature.
So what to do with the extra A/D converter? Using it as a second
pathway with a different gain or frequency response is overkill as this can
be accomplished by mux. The analog input could be paralleled to both
A/Ds so that one could be used as a backup. This would require only
two lines - one to each output enable so that the two converters could be
connected to the CPLD with only 11 data lines. Is it worth the extra
effort? Probably not.
The final decision is to use four muxes to choose one channel at a time
to feed into a single A/D converter. This will minimize the analog
circuitry, CPLD logic, board space, design time, and debugging.
|Wed Jun 4 20:21:13 2008 Trey Brown
A nice secondary function is Loss of Back Wall on compression (OD
grinds, STEALTH Flaws). Not to say that it would be a Feature
Creature but should be incorporated in the future.
Wed Jun 4 20:32:14 2008 Mike Schoonover
I think that feature might actually be primary - it will have to be
added before first run.
June 2, 2008
New Contributor Announcement
are pleased to announce that Curt Irvin has joined the team as a
contributing member! Curt is an ex Navy Submarine Sonar Tech and has
worked in various industries, including oilfield inspection. Curt has
experience with board design, Programmable Logic Controllers, and software.
Most importantly, Curt brings a disciplined, positive approach to project
flow and development.
Please join us in welcoming Curt aboard!
|Tue Jun 3 15:23:11 2008 Rick
Welcome aboard. Glad to have you involved in this exciting project.
Look forward to working with you on this joint development project.
Tue Jun 3 20:23:12 2008 Trey Brown
Welcome Curt! I am sure you will enjoy working with all of us. Glad
to have you on the team.
Wed Jun 4 17:45:55 2008 Daryl Bolen
Welcome Curt, great to have you aboard!
June 1, 2008
Chassis ORBs and BNC Connectors
The Option Retaining Bracket (ORB) G149 from
Globe Brackets has been selected.
It has four BNC mounting holes spaced evenly with LED holes near each one.
The BNC Connector AMP #5227161-6 seems to be a match for the
ORB and has a plastic body so it will be isolated from the chassis.
Digi-Key A32259-ND Connector, BNC, Right Angle, PCB
Mount, Gold Plate Center Pin, Black VALOX, 0.625 mntg ht, with
mounting posts, AMP #5227161-6
|Tue Jun 3 15:27:38 2008 IRNDT
Want to ensure everyone is aware that the connector chosen for the
transducer connectors is the Lemo connector ERN.00.250.NTL
This connector was selected as the best suited for long periods of
Tue Jun 3 15:54:49 2008 Mike Schoonover
Re: Lemo connector
Ok, now it's on the record - good to see that one is resolved.
We also need to decide on the size of the coax and try to maintain
consistency with each unit. Different sizes on one unit is OK when
necessary, but we will probably benefit from consistency.
I hope that we can use standard BNCs throughout the system except at
the transducer. They are much easier to work with. We will all need
to be in on the design of the system cabling. The BNCs all need to
be isolated from chassis and frame throughout the system, grounding
those items with a separate connection. This will help immensely
with the "noise demons".
Tue Jun 3 19:51:09 2008 IRNDT
I personally have never seen the benefits of the RG58 cable. It is
bulky and harder to work with than the smaller, shear wave type
cable, and I have never seen a need for pre-amps at the head either,
but what do I know, anyone with a differing opinion jump on in.
I will say this, any BNC connector WILL be crimped and soldered, not
a twist on (in my humble opinion). It is worth the extra bucks cause
the screw on connectors ultimately loosen and crosstalk. You wanna
chase some ghosts, find that on a forty channel system with channel
3's wall pulse causing noise on channel 38's longitudinal. Pack a
lunch is all I can tell ya.
Tue Jun 3 20:30:22 2008 Trey Brown
RG174 is best in our experience due to compact size and 50 0hm. Keep
in mind...length has a great deal to do with signal to noise ratio
in coax. Approx. 100ft lengths in general works well.
Tue Jun 3 20:48:42 2008 Mike Schoonover
I think we can all agree that RG174 is the best choice, at least
in ~100 ft lengths. I also think we can all agree that
solder/crimp BNCs are a definite must.
Proposed UT System Design Guidelines:
1) All ultrasonic cabling: RG174
2) Maximum recommended cable length pulser to transducer: 100 ft
3) All BNCs: solder/crimp, standard size, isolated from
4) Transducer connector: Lemo ERN.00.250.NTL
Wed Jun 4 20:32:11 2008 T Ray
RG174 it is. Even though the distance from the transducers to the
electronics package is less than 100ft, the cables should be 100
anyhow. If anyone disagrees...?? We found it works best by default.
June 1, 2008
The Capulin UT boards must operate in both stand-alone and
in-system modes. Before designing the board, it is necessary to know
the type of chassis they will be integrated with.
A complete ultrasonic inspection system often has 40
channels. This will require 10 Quad Channel UT boards plus one Control
I/O board. The C9000 chassis shown below is available from
Source and has 20 slots.
Unfortunately, the slots are on 0.8" spacing and we will
need at least 1.5" spacing for the boards as they will be approximately 1.0"
tall with the Rabbit module and the pulser power supply mounted. If we
use every other slot, this should give us the needed space for the 10 UT
The Control I/O board could either be mounted off of the
motherboard or made shorter to avoid conflict with the Rabbit and supply
which will be mounted at the rear of the UT boards - it might then be placed
between two UT boards if we can figure out how to mount the Rabbit on the
Control board itself such that it does not conflict with its neighbor.
It may be that the Rabbit can be placed at top rear and the
power supply at top middle on the UT boards. Then the Control board
might be made vertically shorter but horizontally longer, with its Rabbit module protruding out past
the end of the UT boards and thus avoiding conflict.
The motherboard will only provide power and a single
two-wire connection to allow the Control I/O board to send a synchronizing
signal to each UT board so that multiple channels can be fired
simultaneously in bank mode. The signal will be received on each UT
board via opto-isolators to avoid ground loop problems. With this few
connections being made, the Control I/O board can be easily mounted off the
motherboard and connected with jumpers if it absolutely cannot be fitted on
the motherboard itself.
The data communication between the Control I/O board and the
UT boards will be via Ethernet. The synchronizing signal will be
hardwired through the motherboard because it must be more precise than the
timing of Ethernet will allow. The Ethernet switches can be placed in
the drive bays.
The four transducer BNC's will be mounted on the rear of
each UT board so that they are accessible from the back of the chassis.
The connector on the motherboard will be a DIN 41612 style connector as they
are rugged and simple. The DIN 41612 connector with power blade pins
will not be used as it is harder to assemble. If the cards are too
high when plugged into the motherboard, they will be shaped so that the rear
end drops down past the edge of the motherboard so that the ORBs line up
with the slots in the chassis.
The advantages of using such a chassis are many:
power supply available (may need more voltage to fire
the pulser power switch - may have to add a small auxiliary supply)
cooling fan already installed
rack mount - can be mounted in a desktop chassis if
Option Retaining Brackets (ORBs) to mount the four BNC
connectors are commercially available or can easily be fabricated
requires minimum custom work
looks professional and industrial
It is probable that we will need to have one of these
chassis in hand before finalizing the board design to make sure everything
Rack heights measured in Rack Units
(RU or U) = 1.75" / 44.45mm
Chassis width measured in Horizontal
Pitch (HP) = 0.2" / 5.08mm
Option Retaining Brackets (ORBs) -
the bracket on the back of desktop computer plug-in boards that
usually have connectors on them visible from the back of the chassis
A universal backplane is available from
Schroff which might provide an
off-the-shelf solution, saving some design and assembly time. The
connector spacing is 4HP, which is the same 0.8" spacing as the slots in the
above chassis. The backplane has 21 connectors, one more than there
are slots in the chassis. By purchasing the two-layer backplane, the
extra connector could surely be cut off if necessary to fit in the chassis.
The four layer choices won't be used because cutting off the
extra connector could cause shorting if the inner layers are ground planes -
the foil at the cut edge tends to fold over. The 64 pin connector will
be used because it should be cheaper and provides plenty of pins.
Multiple pins will be ganged to supply power. The wire wrap pins and
blade connectors on the bottom can be snipped off or bent over to reduce the
overall height if necessary.
A small, simple board with terminal lugs can be made which
plugs into one of the unused slots to feed in power.
The following is probably the best choice:
||Grid Dimension 5.08 mm
||at each slot
||Adapter fields for connections
||through-connected from connector to connector
|Tue Jun 3 20:44:09 2008 Trey Brown
Good choice at this point. Looks PRO of course.
The point made as far as EXTRA POWER is valid. My experience with a
system which only had 8 pulser receiver boards per chassis, had
drawn too much current thru the standard power connectors on the
mother board. Therefore, a terminal strip was added to handle
Tue Jun 3 21:03:55 2008 Mike Schoonover
I had no idea 8 pulser boards would pull that much current!
The extra power supply I mentioned is only because the pulser switch
might require 15 volts to trigger. Standard PC supplies only deliver
5V and 12V. I don't think we'll need it after all - we should be
able to put a divider on the pulser voltage and get it that way. May
have to install different resistors for different voltage supplies
installed - we will make the resistors pluggable.
The motherboard shown is said to have "power" for each slot - I
think there are tabs for each connector. In the next phase, we will
replace the off-the-shelf board with our own and design in plenty of
power handling, distributing it right to each connector via tabs
from a terminal block as you have suggested.
June 1, 2008
Board Layout Design Rules
The industry standard design rules for board layout
regarding pad and hole sizes are geared towards mass production and not so
much for industrial use. These standards stress the use of the
smallest possible pad and hole sizes which decreases the amount of solder
and heat required for assembly and minimizes the area required by the
Unfortunately, in low quantity industrial use (LQIU) these
standards make it difficult to hand assemble and repair boards. It is
very convenient to be able to accomplish these tasks in house as it takes
time to get a board to and from a fab/repair shop.
For QFP packages, the copper pads are usually covered by the
device pins. The solder paste is meant to be placed on the pad under
the pins and then melted in an oven.
For hand assembly, it is difficult to get the right amount
of paste on the pads and then even harder to get the component positioned
correctly on top without smearing. It is easier to position and fix
the component on dry pads and then spread paste along the outside edges of
the pins, using a heat gun for soldering. A soldering iron can then be
used to reflow any problem areas or remove bridging between pads. If
no pad protrudes beyond the pins, it is harder to get a good solder flow.
To alleviate this problem, we are altering all layout
packages for SMD devices so that at least 1mm extra of the pad is
accessible. Also, we will be using larger hole and pad sizes for
through-mount components to allow easier removal without destroying or
lifting the pad.
|Fri Jun 6 15:39:45 2008 T Ray
Having recently replaced surface mounted ICs, larger pads and holes
would be to our advantage as well as our customers who wish to make
The less surface mount components, the better in my opinion. But,
considering real estate, some discrete components should be SMD.
How economical is it to do both as opposed to one or the other?
Tue Jun 10 01:13:14 2008 Mike Schoonover
Unfortunately, SMD is going to be prevalent on the Capulin boards
for three reasons:
1) Most complex chips such as DSPs and CPLDs are only available in
the SMD form factor.
2) The SMD form factor saves a great deal of board space.
3) SMD components work better with high frequencies as they emit
In general, it is best to avoid mixing SMD and through-hole
technologies from a manufacturing standpoint. It takes twice the
work to assemble a mixed board.
On the plus side, an SMD resistor or diode can be removed very
quickly and with minimal damage if two soldering irons are used. A
through-hole mount component can usually be replaced three or four
times before the pads are destroyed while SMD pads will often
survive much longer if the application of heat is done in a timely
May 31, 2008
Schematic Capture and Board Layout
|We are going to use Eagle schematic capture and
board layout software from
We have used OrCad/Cadence on previous
projects, but the cost of that package is quite high. The
Eagle product is about the only serious, low-cost alternative for
less than $1,500 per seat. This will allow us to provide
software to our contractors at a reasonable price.
The Eagle sales rep assured us that the package can do everything
we need. In addition, a simple version is available free for
evaluation. We are using the free version to create the
components and for experimenting before we license the full package.
The free version only allows one schematic page and two board
layers - BUT - it will display schematics of any size created by the
paid version. So by downloading the free version, anyone can
view and print the schematics we will be creating.
By the time this project is over, we will have a pretty good idea
of the capabilities of the Eagle software. Check back to see
how it works out!
|Fri Jun 6 16:03:01 2008 T Ray
Eagle has not landed. Apparently, It has a problem with VISTA. I
will look further and advise.
Tue Jun 10 01:18:55 2008 Mike Schoonover
Good to know.
Of course they will eventually get that worked out - hopefully soon!
As you are our de facto Vista expert (since you are actually
using/fighting that system) please keep us up to date.
May 30, 2008
Pulser Power Supply and Switch
American Power Designs' X Series switching power supplies have been
selected to provide the pulser voltage. The X series are enclosed in a
metal can to reduce EMI and can produce up to 30 watts. The X30 (30
watts) version is huge - 3" x 2.5", with the X20 being the same size.
As some of the transducers that will be utilized with this project have a
very large surface area, it has been decided to plan for the maximum
The largest voltage available is 1000V, obtained by placing the two 500V
outputs of the X30 500/500 supply in series.
To hasten the design process, it was decided to use the same switch for
the pulser voltage that American Power Designs uses inside their supplies -
the IRFBC20, good for up to 600V. Since they only have to switch
500V for the split supply, they don't use a switch good for the maximum of
1000V when these supplies are put in series.
Due to this limitation, it has been decided to use the X30 200/200
supplies. Jumpers will be designed on the board to allow the supply to
provide a positive or negative going pulse and to select between 200V or
400V. For 200V, the supplies will be paralleled, for 400V they will be
placed in series.
If different voltages are needed, the appropriate X30 supply can be
installed on the board as all products in the series have the same
footprint. The choices are (taking into account the 600V limit of the
switch): 50, 75, 100, 150, 100, 150, 200, 300, 200, 400, & 500 volts.
American Power Designs also uses IRF740 (400V) in some of their supplies.
|Sat May 31 06:02:23 2008 T Ray
In our experience with KB 6000; 200 or 300 volts was too much for
the switches. Although, I think 200 is optimum, my tech turned the
voltage down to 150 with very little drop in DB and eliminated
pulser module failures.
Sat May 31 09:33:39 2008 Mike Schoonover email@example.com
Very interesting, T Ray. Since we won't be using switches, we
might can avoid that problem. The question is: What is the
benefit curve of higher voltages? Can transducers be damaged by too
much? I have seen systems with as much as 1000V pulsers. I also saw
a system where you could tune the voltage and pulse width to exactly
match the impedance of the transducer - eliminating the need for a
damping resistor. This further raises the question: Is bigger
May 29, 2008
More Component Selections Finalized
biggest issue related to choosing the components is operating voltage.
As the A/D converter and DSP use 3.3 volts and this level is available for
the Rabbit Micro Controller and CPLD, this voltage was selected for the
With the voltage and package styles decided, the following component
selections have been finalized:
- RCM4200 - 10/100 Ethernet Rabbit 4000 @ 58.98 MHz
- CPLD XC95144XL-5TQ100C in package 100TQ (1.4mm QFP)
- ADC11DL066CIVS 11 bit, 66 MSPS A/D converter in package TQFP64
- DSP TMS320VC5441PGF in package LQFP176
May 28, 2008
Choosing the Rabbit Micro Controller
it was planned to mount the Rabbit Micro Controller chip and associated
memory and ethernet components directly on the UT board. After
reviewing the extremely economical prices for the Rabbit off-the-shelf
modules, it was instead decided to mount the module onto the board.
There are many Rabbit module versions, using the Rabbit 2000, 3000, and
4000 microcontrollers. Since the expected lifetime of the product is
quite long, it was decided to use the most advanced option - the Rabbit 4000
- as this one will probably be in production the longest.
Only one 4000 module provides 100 Gigabit Ethernet and also happens to
provide the highest speed:
RCM4200 - 10/100 Ethernet Rabbit 4000 @ 58.98 MHz
|Sat May 31 06:11:52 2008 T Ray
The Wabbit..is widely used in our industry as well as others. I have
seen the wabbit for the last 4 years at least.
Sat May 31 09:35:44 2008 Mike Schoonover firstname.lastname@example.org
I never took the Rabbit seriously because I was afraid it was a
small player and would disappear. Time has proven me wrong. The
Ethernet capability is a winner.
May 27, 2008
Choosing Form Factors
the form factor for each component is a critical issue. Cost of
assembly, repair, and debugging are all greatly affected by the component
In the past, a lot of industrial circuit boards used sockets for the IC
chips so that they could be easily changed if necessary. Today's chips
have a much higher pin count and pin density. Although there are
sockets available for some of the new packages, they add a lot of bulk,
cost, and reliability issues.
The main package styles available for the chips in this project are the Quad
Flat Pack (QFP - shown here)
and the Ball Grid Array (BGA). While the QFP pins are accessible for
soldering, examination, and probing, the BGA package pins are solder balls
underneath the package. The QFP packages can be hand soldered while
the BGA requires more complicated assembly procedures. QFP packages
can also be replaced more easily than BGA.
Based on all of these factors, the QFP package has been chosen where
possible for this project.
NOTE: This information has
been partially superseded.
April 10, 2008
Originally, I wanted the DSP to be the only processor on each board and I
wanted to to make each board functional enough that it could act as the I/O
control board. I was hoping to avoid complexity and having to learn
two different processors.
Since there are four channels per board and each DSP has four cores, it
seemed logical to assign one core to each channel. The alternative is
to assign all cores to each channel, with each core handling a different
part of the signal processing in sequence. Thus the data would be
passed from core to core as additional processing is required.
Of these, the first option seems simpler. The same code is uploaded
to each core and there is no need to balance processing between the cores.
For instance, if a new processing algorithm is added when using the second
option one must examine the code for each core to determine the best one to
handle it, making sure that the chosen core is not already overloaded.
If processing must be added to an overloaded core, then some functions would
have to be shifted to the next core.
I had planned to use the Rabbit processor system to learn the details of
ethernet design and then transfer this knowledge to the Capulin system.
The Rabbit is an off-the-shelf single board computer system which has built
in ethernet capability with schematics and source code publicly available.
As mentioned before, I didn't really want to add another processor to the
system and I felt that the Rabbit processor wasn't "serious" enough.
A problem arose in deciding on how to control the ethernet with the DSP.
If each core was assigned to a channel, would each core handle its own
ethernet? How would each core gain access to the ethernet chip? Would
one core handle the additional responsibility of the ethernet? Would
the code for each contain ethernet drivers but only be activated in the
designated core? Wouldn't this make it difficult to gauge the load on
the designated ethernet core? Would it be worth switching to
sequential core processing so that the last core in the series would handle
the ethernet load?
A second problem was that of loading the DSP code. The DSPs do not
load their code automatically, so a bootstrap program was going to have to
be loaded from EEPROM into the DSPs by a CPLD. The bootstrap program
would then load the processing code from the host PC via ethernet.
This allows the processing code to be updated easily by loading new byte
code onto the host. The Rabbit could be used as the bootstrap device,
transferring the processing code from the host into the DSPs using their HPI
ports. Instead of having to re-engineer the ethernet technology AND
devise a CPLD based bootstrap loader, both problems would be solved by just
using the Rabbit.
A third problem was that adding the I/O and control hardware to each UT
board would waste space and money since only one or two boards in each
system would need that functionality. The Rabbit could be used to
create the I/O and data manager board - and would be a better choice than a
DSP due to the fact that DSPs are not designed for I/O control.
Main advantages for the Rabbit:
ethernet ready with drivers and schematics
built in bootstrap code loading
better suited for I/O control
more economical than a DSP
March 3, 2008
There are a couple of Pulser/Receiver boards on the market which use the
USB interface. Unfortunately, USB employs a Master/Slave oriented
format wherein each board can only talk to one Master - the host PC.
The Capulin system will make use of an interface controller which will
collect data from multiple pulser/receiver boards to be transferred to the
host PC, reducing the load on the PC. Ethernet allows any board to
communicate with any other board or with the host PC itself.
By using an ethernet switch to connect the boards, the data
traffic is routed directly from the sender to the receiver and can even be
isolated to a specific set of boards. This allows the PC to
communicate with printers and other PCs without mixing data and causing
Another big advantage for ethernet is the plethora of
off-the-shelf equipment. Transmitting over large distances is no
problem, and fiber optic links can even be used.
March 1, 2008
No Closed Source Third Party Java Code
Third party code holds the promise of a quick fix.
Until it's time to upgrade. Whenever it becomes desirable to move to
the next compiler version or even a new version of any of the third party
code, the upgrade often requires extensive repairs to make all of the
modules work together. Since source code is rarely available, the
programmer is dependent on the vendor to make any bug fixes.
Often an upgrade must be delayed until each and every vendor
updates their respective modules. Worse, the code may be discontinued
at any time.
It's just not worth it.
February 25, 2008
Why not Visual Programming Design?
The Java developer kit provides a visual programming environment, but all
the code for this project is in plain text. This makes it very simple
to transfer code back and forth and more compatible with version control
software. Visual program elements almost always require additional
files to define the objects and these add additional code burdens.
February 17, 2008
The arguments about which language to use are as varied as the
programmers who make them. Java's only real negative is that it is an
interpreted language which makes it a tad slower than C++.
Having programmed in BASIC, FORTRAN, COBOL, PASCAL, C++, and PERL, I have
found Java to be a very tidy language. Best of all, the GUI is tightly
integrated into the language instead of being glued together like every C++
rendition with a crudely tacked on visual design interface.
Here are a few reasons why Java was chosen:
- the GUI is tightly integrated
- cross platform
- a lot of features are included in the core package
- the byte code is compact
- ethernet and Internet ready
- eliminates many error prone programming concepts
- the developer packages are FREE!
February 12, 2008
The following design components have been selected:
February 8, 2008
The following design criteria shall be used:
- the front end software shall be Java
- the boards shall be stand-alone and not plugged into the PC
- ethernet shall be used to communicate with the boards
- each board shall have four UT channels
- each board shall have a pulser capable of 300V
- each board shall have a rep rate of 2K for each channel, 8K overall
- each board shall collect peak data for transmission to the host PC
- each system of several boards shall be able to bank fire multiple
transducers at once, one channel from each board, with the firing
occurring simultaneously to avoid crosstalk
February 4, 2008
Why Open Source?
Traditionally, companies have guarded their source code and schematics.
In recent years, the concept of open source has begun to take hold.
Java, Mozilla, and Firefox are good examples of open sourcing. It is
just very recently that for-profit companies have embraced the open source
If open source materials are used in a project, then it is required by
the license for that project to be open source as well. By starting
the project as open source in the beginning, it allows the use of existing
open source code to speed development.
While some might fear that their technology will be stolen, this rarely
proves to be a problem. Generally, any company that can make use of
such technology is fully capable of developing it independently. Due
to the "not invented here" philosophy, most developers have a difficult time
employing outside code.
Open source has several advantages:
- it allows the use of other open source materials
- outside persons often provide help or hints
- a purchaser often feels much better about a product for which he has
access to abundant information
February 2, 2008
There are many books which have contributed ideas and ideals to this
project. A few have particular meaning for the project and can be
found at Amazon or Barnes & Noble:
Dreaming in Code, Rosenberg (a must read for project managers)
C++ In Action, Milewski (brilliant programming for brilliant programmers)
Digital Signal Processing (the best book on the subject)
January 20, 2008
This project has been in the "blue sky" phase for nearly 6 years.
The time has come to put thoughts to paper, schematic, and layout.
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