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Mike Schoonover, hardware & software
Zenaido Delgado, UT alpha testing
Trey Brown, technical
Daryl Bolen, controls
Rick Girndt, ultrasonic
Curt Irvin, hardware & software
Fiona Zhang, software
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The

   Capulin

         Project

 

Pulser Receiver Board


December 10, 2008                Overview

The pulser/receiver (UT) board handles up to four transducers and provides pulsing, receiving, filtering, data manipulation, and peak detection.  The peak data recorded is sent to the master or the host PC when requested, at which time the stored peak is reset and a new peak recorded.

Each UT board has the following main components: The Rabbit sets up and controls the UT board and provides communication between itself and the master controller and the host PC.  Upon system startup, the host PC transmits setup data and DSP software directly to each UT board.  During operation, the master collects data from each UT board and combines it into a packet for transmission to the host PC.  This reduces the traffic to the host PC.  Since the communication is via ethernet, any board or host can communicate with any other board or host.

Startup

On startup, the Rabbit initializes the board with basic settings.  The Rabbit is able to access the DSP Host Port Interface (HPI) through the FPGA, as well as several control registers.  It is also able to communicate with each of the four DSP cores via serial data ports funneled through the FPGA.

The host PC transmits the DSP software to the Rabbit which in turn loads it into each DSP core's memory via the HPI.  In the future, the host PC may be able to transmit code updates for the Rabbit itself to be stored in flash ram so that this code may also be updated remotely.

The host PC then transmits configuration data to the Rabbit such as programmable hardware gains, software gains, filtering parameters, gate information, and sample window timing.  These are then transmitted to the DSPs via the HPI and to the programmable gain chips via a serial data connection through the FPGA.

The serial data connection lines to the programmable gain chips are passed through the FPGA as raw inputs and outputs to registers accessible by the Rabbit.  The Rabbit sends data by directly controlling these lines through the FPGA registers.  As these setups are non-critical in regards to speed, this is an acceptable arrangement.  The DSP serial ports are actually processed by the FPGA to convert the data stream into bytes available to the Rabbit.  This data is collected during full speed operation and must be done as quickly as possible.

The following registers are designed into the FPGA for access by the Rabbit:

    Master Control, address 0x00
        write only

    Reset, address 0x01
        write only

The board has two DSP chips with four DSP cores in each.  The reset pins from each chip are tied together, so each chip is Reset simultaneously, as are the DSP A core in each, the DSP B core, the DSP C core, and the DSP D core.

    LED Display, address 0x02
        write only

Bits 0:7 control LEDs 0:7.

    Normal Mode:

    Debug Mode:

Button 1 on the UT board switches between debug modes, which are as follows:

    Debug Gain Adjust Mode:

Note: These gains are the programmable gain hardware chips.

    Debug A/D Data Monitor Mode:

Button 2 cycles through the four transducers, displaying the raw A/D data for the selected transducer on the LEDs.

Note: The buttons are read and modes and LEDs set by the Rabbit except where the LEDs are monitoring raw data.  The FPGA is not programmed to process switch inputs, mode changes, etc - it merely passes them onto the Rabbit.  For raw data, the input latches are connected to the LED outputs by a flag set in the FPGA by the Rabbit.

    Rep Rate Delay Registers, addresses 0x03, 0x04, 0x05, 0x06
        write only

This register provides a delay between the firing of each transducer time slot to achieve the desired rep rate.  This delay is only used if the board is designated to be the source of the rep rate signal, i.e. bit MasterControl:1 = 1.

    Control Inputs 1 Register, address 0x07
        read only

    Board Address Inputs Register, address 0x08
        read only

Used to set an address for the board to identify it uniquely on the ethernet.  The board and chassis addresses are concatenated and used as the lowest byte of the ethernet address.  These inputs come from switches on-board or inputs from off-board.  If the switches are set to address 0 they can be overridden by inputs off-board, such as switches on a motherboard.

    DSP HPI Address Registers
        DSP Chip 1: address 0x09 (low), 0x0a (high)
        DSP Chip 2: address 0x0b (low), 0x0c (high)

        write only

NOTE: may not be necessary since HPI Address & Data lines are multiplexed.  Address may be put on Write registers for transmittal to the HPI address register.

Before reading from or writing to the DSP HPI port, the starting address is loaded into these two bytes.  Afterwards the DSP is setup to auto increment the address with each subsequent data byte read or written.  These registers are used by the Rabbit to communicate with the DSP and are only connected to the DSP when the system is not in run mode.

    DSP HPI Data Write Registers
        DSP Chip 1: address 0x0d (low), 0x0e (high)
        DSP Chip 2: address 0x0f (low), 0x10 (high)

        write only

The data word to be written to the HPI is stored in these two registers.  The HPI control lines are then strobed to complete the transaction after setting the DSP HPI Address Registers.  These registers are used by the Rabbit to communicate with the DSP and are only connected to the DSP when the system is not in run mode.

    DSP HPI Data Read Registers
        DSP Chip 1: address 0x11 (low), 0x12 (high)
        DSP Chip 2: address 0x13 (low), 0x14 (high)

        read only

The data word last read from the HPI is stored in these two registers.  The HPI control lines are first strobed to initiate the transaction after setting the DSP HPI Address Registers. These registers are used by the Rabbit to communicate with the DSP and are only connected to the DSP when the system is not in run mode.

    DSP HPI Host Control 1 Register
        DSP Chip 1: address 0x15
        DSP Chip 2: address 0x16

        write only

Strobe lines to control the DSP's HPI port. This register is used by the Rabbit to communicate with the DSP and is only connected to the DSP when the system is not in run mode.

The latch control for the Data Read Registers is also accessible here so that the Rabbit can control when the data from the HPI port is latched.  NOTE: This may not be used - may be automated.

    DSP HPI Host Control 2 Register
        DSP Chip 1: address 0x17
        DSP Chip 2: address 0x18

        write only

Strobe lines to control the DSP's HPI port. This register is used by the Rabbit to communicate with the DSP and is only connected to the DSP when the system is not in run mode.

    DSP HPI Status Register
        DSP Chip 1: address 0x19
        DSP Chip 2: address 0x1a

        read only

Status lines from the DSP's HPI port. This register is used by the Rabbit to communicate with the DSP.

    Sample Start Delay Registers

        Transducer 1: addresses 0x1b, 0x1c, 0x1d, 0x1e
        Transducer 2: addresses 0x1f, 0x20, 0x21, 0x22
        Transducer 3: addresses 0x23, 0x24, 0x25, 0x26
        Transducer 4: addresses 0x27, 0x28, 0x29, 0x2a

        write only

The value placed in these registers specifies the amount of time to delay from the initial pulse of the transducer before data collection is started.  The three registers are concatenated into a 24 bit number.  The delay is usually adjusted to the point just before the interface of the sample wall or the beginning of the first gate.  If interface tracking is in use, the delay must be set before the interface echo so that it will be captured and detected.

This delay is essentially identical to the setting on most UT scopes referred to simply as "Delay".  Its use is important so that useless data is not collected from the time spent traversing the wedge and water path.  Any extra data requires extra transfer and processing time and thus reduces the maximum rep rate.

The delay is based on the clock frequency of the A/D converter.  For a 66 MHz conversion clock, each count in this register equals .01515 uS of delay.

    Sample Count Registers

        Transducer 1: addresses 0x2b, 0x2c, 0x2d
        Transducer 2: addresses 0x2e, 0x2f, 0x30
        Transducer 3: addresses 0x31, 0x32, 0x33
        Transducer 4: addresses 0x34, 0x35, 0x36

        write only

 Caution: This value must be set to an even number or the results will be unpredictable.  The data is transferred from the FPGA to the DSPs in pairs, so the data buffer must contain an even number of samples.

This register specifies the number of samples to be recorded after the start delay has passed.  The value should be chosen such that all data necessary to process the last gate is recorded.  Each sample represents

 1/(Sampling Frequency) in time.

For a 66 MHz sampling clock, this is 1/66 MHz = .01515 us/sample

    DSP HPI Data Block Start Address Registers

        Transducer 1: addresses 0x37, 0x38, 0x39
        Transducer 2: addresses 0x3a, 0x3b, 0x3c
        Transducer 3: addresses 0x3d, 0x3e, 0x3f
        Transducer 4: addresses 0x40, 0x41, 0x42

        write only

These registers specify the starting address in each DSP's memory for the A/D data block to be stored by the FPGA.  The values are setup before initiating the run mode.

    Transducer Setup Registers, address 0x43, 0x44, 0x45, 0x46
        read only

These four registers control how the transducers are handled during run mode: TranSetup1, TranSetup2, TranSetup3, TranSetup4.

Note: For Pulse-Echo mode, channel 1 pulser is fired for channel 1 receive and so forth.  For Pitch-Catch, a different channel can be fired other than the receiving channel.  This allows the UT board to be setup for two Pitch-Catch channels by firing the channel two pulser to pitch and then catching on channel one, etc.  To setup four Pitch-Catch channels, the register is setup the same as for Pulse-Echo, i.e. the same channel is fired as is used for receiving.  For this setup however, the pulser cables on the board are disconnected and new longer cables are added which jump over to a separate set of off-board connectors which fire the Pitch transducers.  The Catch transducers are connected to the inputs on the board, thus the pulsing is separated from the receiving.

For bits 4:7, only the values 0-7 are valid.  Numbers above this will result in no channel being pulsed for the specified transducer.

    Pulser Time Slots Register, address 0x47
        write only

Specifies the number of time slots which are active up to a total of eight.  One or more transducers can be pulsed during each time slot - it is possible to have a time slot during which no transducers are fired.

4 transducers fired sequentially: use 4 time slots, place each transducer in a separate slot in the Transducer Setup registers.

2 transducers fired simultaneously followed by 2 other transducers fired simultaneously: use 2 time slots, place 2 transducers in time slot 1 and two transducers in time slot 2 in the Transducer Setup registers.

2 transducers fired simultaneously, other 2 off : use 1 time slot, place both transducers in time slot 1 in the Transducer Setup registers.

2 transducers fired sequentially, other 2 off: use 2 time slots, place one transducer in time slot 1 and the other in time slot 2 in the Transducer Setup registers.

    and so forth.

Should match the number of transducers specified as active and the number of different time slots specified in the Transducer Setup registers.

If bit 1 of the Master Control register is 0, a delay will be added between each time slot based upon the value in the Rep Rate Delay registers - this establishes the rep rate and an output signal will be pulsed low so that other boards can be synchronized.

If bit 0 of the Master Control register is 1, the firing for each time slot will be delayed until the external trigger sync signal goes low.  This signal may be provided by another UT board or any other timing source.

 After the number of slots specified by the Number of Time Slots register have been fired, the sequence starts over with the first slot.

When fewer channels are active or the echo time is short, the delay between registers must be increased to allow time for the DSPs to process data between shots (i.e. the rep rate is decreased).  When the echo time is long and more channels are fired, the DSPs are able to process each channel during the time the other channels are being pulsed and processed.

    Pulse Width Registers, addresses 0x48, 0x49, 0x4a, 0x4b
        write only

This register provides the width of the transducer firing pulse.  This value is only used if the board is designated to be the source of the rep rate signal, i.e. bit MasterControl:1 = 1.

    Programmable Hardware Gain Registers

        Transducer 1: address 0x4c
        Transducer 2: address 0x4d
        Transducer 3: address 0x4e
        Transducer 4: address 0x4f

        write only

These registers control the ?? busses to the programmable gain chips.

    Pulse Delay after Sync Registers, addresses 0x50, 0x51
        write only

This register sets the delay after the sync pulse is either generated or received, depending on whether the board is the source of the sync signals.  The delay allows the transducer firing pulse to be precisely synchronized between all boards, taking into account delays in the sync and sync reset pulse signal paths.

For instance, the board generating the sync pulse should have a delay before firing its transducers because the other boards will not receive the sync pulse until a short time later due to delays in the isolation devices between the sender and receivers.

    Unused, addresses 0x52, 0x53

    DSP Serial Port Receive Status Register, address 0x54
        read only

Status bits of the 8 DSP core incoming serial ports.  Each port has one bit to specify if data is waiting to be read by the Rabbit.  The bit is not set until a full packet is ready.  The bit is cleared when the first byte of the packet is read.  It is up to the Rabbit code to know how many bytes are in the packet and to read them all.

    DSP Serial Port Transmit Status Register, address 0x55
        read only

Status bits of the 8 DSP core outgoing serial ports.  Each port has one bit to specify if data can be sent by the Rabbit.

    DSP Serial Port Data Read Registers

        DSP Chip 1 - cores A, B, C, D: addresses 0x56, 0x57, 0x58, 0x59
        DSP Chip 2 - cores A, B, C, D: addresses 0x5a, 0x5b, 0x5c, 0x5d

        read only

One byte registers to read data transmitted from each DSP core and stored in a RAM.

The bits in the DSP Serial Port Receive Status Register signal when a packet is ready to be read.  The size of the packet to trigger the signal is set by the Rabbit via the Packet Size Register prior to sending a data request command to the DSP.

    DSP Serial Port Data Write Registers

        DSP Chip 1 - cores A, B, C, D: addresses 0x5e, 0x5f, 0x60, 0x61
        DSP Chip 2 - cores A, B, C, D: addresses 0x62, 0x63, 0x64, 0x65

        write only

One byte registers to transmit data to each DSP core.

The bits in the DSP Serial Port Transmit Status Register signal when the next byte can be written.

    DSP Serial Port Packet Size Registers

        DSP Chip 1 - cores A, B, C, D: addresses 0x66, 0x67, 0x68, 0x69
        DSP Chip 2 - cores A, B, C, D: addresses 0x6a, 0x6b, 0x6c, 0x6d

        write only

The Rabbit sets this register to specify the number of bytes to be received to form a complete packet from the DSP.  When this number of bytes has been received, the appropriate bit will be cleared in the DSP Serial Port Receive Status Register.

The Rabbit should set this register prior to requesting a data packet from a DSP.  If the packet size never changes, this register may be set once at the beginning and never changed.

    Sync Pulse Width Registers, addresses 0x6e, 0x6f
        write only

This register provides the width of the sync pulse which synchronizes the transducer firing pulses for all boards in the system.  This value is only used if the board is designated to be the source of the rep rate signal, i.e. bit MasterControl:1 = 1.  This value should be wide enough to meet minimum requirements of any isolation devices in the signal path.


Author: Mike Schoonover

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