Mike Schoonover, hardware & software
Zenaido Delgado, UT alpha testing
Trey Brown, technical
Daryl Bolen, controls
Rick Girndt, ultrasonic
Curt Irvin, hardware & software
Fiona Zhang, software
You (yes, you!)
Java Source Code
Rabbit Source Code
DSP Source Code
Layout Tutorial and Project Design Guidelines
ICAP/4 RX Tutorial
Things we are working on adding or fixing!
Quips, Quotes, &
December 10, 2008
This is an overview of various timing data and specifications for the
pulser/receiver board and the overall system.
A/D sample rate: 66.666666 million samples/sec
A/D sample rate period: 0.015 us : 15 ns
The A/D clock is used to drive the A/D converters, the FPGA, and the DSP.
Minimum period for clock in of the DSP: 20 ns
Since the A/D clock is too fast for input to the DSP, it will be divided by
two in the FPGA to obtain a 30 ns period. Inside the DSP, it will be
multiplied by 3 by using the PLL to obtain a 10 ns period.
Actual clock period of the DSP: 10 ns
Author: Mike Schoonover
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